As is known in the art, analog-to-digital converters (ADCs) convert a signal in analog format to a signal in digital format. Conventional ADC circuits can have a variety of circuit architectures, each of which has certain concomitant advantages and disadvantages. Known ADC architectures include pipeline, sub-ranging, sigma-delta, cyclic, flash, successive approximation, and dual-slope. Each architecture is generally applicable to a limited operating range. That is, each of these architectures has strengths and weaknesses that make them more amenable to working in certain ranges of frequency and resolution.
Pipelined ADCs use the successive-approximation algorithm, but perform the required comparisons sequentially in successive stages rather than in a single stage as in the classic successive-approximation architecture. The pipelined architecture trades off circuit complexity in favor of increased sample rate; an N-bit pipelined ADC is approximately N times as fast as an N-bit successive-approximation ADC, while demanding at least N times as much circuit complexity. This tradeoff is advantageous for applications requiring relatively high resolution (N≧8) combined with relatively high sample rate. ADCs employing the pipelined architecture can be implemented using several basic circuit technologies including charge-domain (CCD) technology.
Prior-art charge-domain pipelined ADCs have been limited in precision to approximately ten bits. One reason for this limit is the difficulty of precisely comparing charges. A second limit on increasing precision arises from two considerations. One consideration is that the quantity of charge used to represent the signal in a charge-domain ADC must be increased in proportion to the square of the desired signal-to-noise ratio, as shown by the following equation:QSIG∝22N  (Equation 1)where N is the number of bits of resolution of the ADC.
A second consideration is that the gate capacitance of the CCDs employed in the ADC must be increased proportionately to accommodate the signal charge. For a given fabrication process, increasing the gate capacitance requires an increase in gate length (L), gate width (W), or both. Increasing L reduces the CCD charge-transfer speed, thus limiting the maximum sample rate of the ADC. This tradeoff is unacceptable in many cases, so W must be increased.
The extent to which W can be increased, however, is limited by dynamic effects. The gate clock voltages and signal charge must propagate along the width of the CCD gates. Thus, increasing W slows these signals and again limits the sample rate of the device. For this reason, the potential for increasing W is limited for any particular sample rate.
Because charge transfer in CCDs occurs only between contiguous gates, the required charge-domain ADC operations of conditional charge transfer (also referred to as charge steering) and charge merging involve changes in the direction of charge flow. As gate area is increased to accommodate larger signal charge, the CCD structures for these functions must increase in both L and W. As before, these increases in L and W reduce charge-transfer speed, and thus are limited for any particular sample rate.